For example, U.S. Pat. No. 7,064,018-B discloses a semiconductor integrated circuit having a logic circuit and a thin film transistor (TFT) circuit provided in a layer above the logic circuit.
In such semiconductor integrated circuit, an interlayer insulating film is formed on the logic circuit, and an amorphous silicon layer is formed on the interlayer insulating film. A TFT circuit is formed using the amorphous silicon layer as an active region. The logic circuit and the TFT circuit are connected by a contact plug penetrating the interlayer insulating film.
If the amorphous silicon layer as an active region of the TFT circuit is connected with the contact plug formed of tungsten (W), electric-resistance therebetween will be high. Consequently, the amorphous silicon layer has fully been silicided to reduce the connection electric-resistance between the active region (fully-silicided amorphous silicon layer) of the TFT circuit and the contact.
However, the adhesiveness between the fully-silicided amorphous silicon layer and the interlayer insulating film (on which the amorphous silicon layer is formed) is low. If the amorphous silicon layer is fully silicided, the fully-silicided amorphous silicon layer may peel off the interlayer insulating film, and the yield of the device may be reduced.